luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
OpenRAM/technology/scn4m_subm
History
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 		2020-11-13 10:07:40 -08:00
..
gds_lib Rework bitcells. 2020-11-13 10:07:40 -08:00
mag_lib Rework bitcells. 2020-11-13 10:07:40 -08:00
models Adjusted vth0 of FF and SS models in scn4m from nominal. 2019-10-07 15:26:20 -07:00
sp_lib Rework bitcells. 2020-11-13 10:07:40 -08:00
tech Rework bitcells. 2020-11-13 10:07:40 -08:00
tf Add draft lyt file -- connectivity not working 2020-08-14 10:38:22 -07:00
__init__.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00