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OpenRAM/compiler/bitcells
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mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 		2020-11-13 10:07:40 -08:00
..
bitcell_1port.py Rework bitcells. 2020-11-13 10:07:40 -08:00
bitcell_2port.py Rework bitcells. 2020-11-13 10:07:40 -08:00
bitcell_base.py Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
col_cap_bitcell_2port.py Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
dummy_bitcell_1port.py Rework bitcells. 2020-11-13 10:07:40 -08:00
dummy_bitcell_2port.py Rework bitcells. 2020-11-13 10:07:40 -08:00
dummy_pbitcell.py Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
pbitcell.py Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
replica_bitcell_1port.py Rework bitcells. 2020-11-13 10:07:40 -08:00
replica_bitcell_2port.py Rework bitcells. 2020-11-13 10:07:40 -08:00
replica_pbitcell.py Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
row_cap_bitcell_2port.py Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00