..
__init__.py
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2022-07-13 15:55:57 -07:00
channel_route.py
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2022-07-13 15:55:57 -07:00
contact.py
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2022-07-13 15:55:57 -07:00
delay_data.py
Update copyright year.
2021-01-22 11:23:28 -08:00
design.py
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2022-07-13 15:55:57 -07:00
errors.py
Add exception errors file
2020-04-08 16:55:45 -07:00
geometry.py
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2022-07-13 15:55:57 -07:00
hierarchy_design.py
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2022-07-13 15:55:57 -07:00
hierarchy_layout.py
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2022-07-13 15:55:57 -07:00
hierarchy_spice.py
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2022-07-13 15:55:57 -07:00
lef.py
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2022-07-13 15:55:57 -07:00
logical_effort.py
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2022-07-13 15:55:57 -07:00
pin_layout.py
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2022-07-13 15:55:57 -07:00
power_data.py
Update copyright year.
2021-01-22 11:23:28 -08:00
route.py
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2022-07-13 15:55:57 -07:00
timing_graph.py
Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.
2021-09-07 15:56:27 -07:00
utils.py
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2022-07-13 15:55:57 -07:00
vector.py
Fix missing hash recompute in vector class.
2022-05-17 13:30:41 -07:00
vector3d.py
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2022-07-13 15:55:57 -07:00
verilog.py
Move mem reg before usage for compatibility
2021-10-13 09:46:02 -07:00
wire.py
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2022-07-13 15:55:57 -07:00
wire_path.py
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2022-07-13 15:55:57 -07:00
wire_spice_model.py
Added unit r and c values with m2 minwidth incorporated to match CACTI params
2021-08-01 00:23:59 -07:00