Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
c260297366f5724e9cdab51e493b175beb8d8358
OpenRAM/compiler/example_configs
T
History
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once.
2020-07-13 12:49:24 -07:00
..
big_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_1rw_1r_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_1rw_2mux_scn4m_subm.py
Make drc and lvs errors a member variable. Run only once.
2020-07-13 12:49:24 -07:00
example_config_1w_1r_scn4m_subm.py
Remove old drc/lvs override name
2019-12-16 10:05:52 -08:00
example_config_freepdk45.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
example_config_scn4m_subm.py
revert example scn4m to non netlist only
2020-02-09 23:52:11 -08:00
giant_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
medium_config_scn4m_subm.py
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
Powered by Gitea Version: 1.27.2 Page: 151ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API