Matt Guthaus 68b30d601e Move bitcells to their own directory in preparation for custom multiport cells.		2018-10-05 08:09:09 -07:00
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pgate.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
pinv.py	Fixed known typos of the word transition.	2018-09-10 14:27:26 -07:00
pinvbuf.py	Make bitcell width/height not static. Update modules to use it for pbitcell.	2018-09-04 11:55:22 -07:00
pnand2.py	Fixed known typos of the word transition.	2018-09-10 14:27:26 -07:00
pnand3.py	Fixed known typos of the word transition.	2018-09-10 14:27:26 -07:00
pnor2.py	Fixed known typos of the word transition.	2018-09-10 14:27:26 -07:00
precharge.py	Move place function to instance class rather than hierarchy.	2018-08-27 17:25:39 -07:00
ptx.py	Converted all modules to not run create_layout when netlist_only	2018-08-27 16:42:48 -07:00
single_level_column_mux.py	Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.	2018-09-09 22:06:29 -07:00