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base
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Fix instersection bug. Improve primary and secondary pin algo.
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2018-12-04 16:53:04 -08:00 |
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bitcells
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Bitcell supply routing fixes.
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2018-11-30 12:32:13 -08:00 |
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characterizer
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moved system call to datasheet.info generator
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2018-12-05 17:35:35 -08:00 |
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datasheet
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removed placeholder data
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2018-12-06 10:17:12 -08:00 |
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drc
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Moving wide metal spacing to routing grid level
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2018-10-15 09:59:16 -07:00 |
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gdsMill
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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modules
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Bitcell supply routing fixes.
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2018-11-30 12:32:13 -08:00 |
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pgates
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pgate inputs and outputs are all on M1 for flexible via placement when using gates.
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2018-11-28 12:42:29 -08:00 |
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router
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Round output to look pretty
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2018-12-04 17:08:47 -08:00 |
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tests
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fixed config file path
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2018-12-06 09:26:38 -08:00 |
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verify
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Remove redundant DRC run in magic.
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2018-11-05 13:30:42 -08:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Remove options from example config files
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2018-11-05 12:47:47 -08:00 |
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example_config_scn4m_subm.py
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Revert to 5V example until we fix spice models in scn4m_subm
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2018-11-27 14:17:06 -08:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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git_id
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track git_id
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2018-12-05 16:13:52 -08:00 |
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globals.py
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added warning to test 30 coverage is not installed
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2018-12-03 13:24:22 -08:00 |
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openram.py
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moved system call to datasheet.info generator
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2018-12-05 17:35:35 -08:00 |
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options.py
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Simplifying supply router to single grid track
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2018-12-04 08:41:57 -08:00 |
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sram.py
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merged branch wtih dev
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2018-12-03 09:47:34 -08:00 |
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sram_1bank.py
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Convert channel router to take netlist of pins rather than names.
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2018-11-29 12:12:10 -08:00 |
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sram_2bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_base.py
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Fix SRAM level control routing errors.
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2018-11-28 15:30:52 -08:00 |
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sram_config.py
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Added custom 1rw+1r bitcell. Testing are currently failing.
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2018-10-22 17:02:21 -07:00 |
bf27eb8cd6