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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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beef9441b72dc8ac045f806bbeb4c2711310be61
OpenRAM/compiler/sram
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mrg f358de78bb Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
2020-04-03 13:39:54 -07:00
..
sram_1bank.py
Route RBL to edge of bank.
2020-03-06 09:03:52 -08:00
sram_2bank.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
sram_base.py
Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
2020-04-03 13:39:54 -07:00
sram_config.py
s8 gdsless netlist only working up to dff array
2020-02-09 21:37:09 -08:00
sram.py
PEP8 Formatting
2020-03-05 16:20:21 -08:00
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