mrg 5f3a45b91b Compute bus size separately for ports		2020-06-29 05:54:30 -07:00
..
sram.py	Fix lvs_write in sram class	2020-04-06 15:20:59 -07:00
sram_1bank.py	Compute bus size separately for ports	2020-06-29 05:54:30 -07:00
sram_2bank.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
sram_base.py	Add correct boundary to SRAM	2020-06-14 14:17:35 -07:00
sram_config.py	changes to support spare columns	2020-04-14 03:09:10 +00:00