Bugra Onal 3496ac8f5a Added buffer to sense_amp output (need to resize)

2023-02-21 13:23:29 -08:00

..

gds_lib

Move power pins to horizontal or vertical layer in all cells.

2022-03-31 16:36:19 -07:00

mag_lib

Rework bitcells.

2020-11-13 10:07:40 -08:00

models

Adjusted vth0 of FF and SS models in scn4m from nominal.

2019-10-07 15:26:20 -07:00

sim_data

Added more data for regression modules.

2021-06-21 17:21:00 -07:00

sp_lib

Added buffer to sense_amp output (need to resize)

2023-02-21 13:23:29 -08:00

tech

Update copyright year

2023-01-28 22:56:27 -08:00

tf

Add draft lyt file -- connectivity not working

2020-08-14 10:38:22 -07:00

__init__.py

Fix path to tech and spice models.

2023-02-17 17:32:30 -08:00