mirror of https://github.com/VLSIDA/OpenRAM.git
Add back gating of w_en since write should happen in second half or else we will have write and precharge simultaneously active. |
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| .. | ||
| pbitcell.py | ||
| pgate.py | ||
| pinv.py | ||
| pinvbuf.py | ||
| pnand2.py | ||
| pnand3.py | ||
| pnor2.py | ||
| precharge.py | ||
| ptx.py | ||
| single_level_column_mux.py | ||