Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-01 18:48:10 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
bae83fc686ef595ee02fb6b865b7da77bc41ef5c
OpenRAM/technology/scn3me_subm/mag_lib
T
History
Matt Guthaus 6f8744712d Add extra pwc to 6T SCMOS cell.
2018-02-05 14:44:15 -08:00
..
cell_6t.mag
Add extra pwc to 6T SCMOS cell.
2018-02-05 14:44:15 -08:00
ms_flop.mag
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
replica_cell_6t.mag
Add extra pwc to 6T SCMOS cell.
2018-02-05 14:44:15 -08:00
sense_amp.mag
Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments.
2018-01-24 13:02:55 -08:00
tri_gate.mag
Fixed bug with missing tri gate via.
2018-01-29 17:29:30 -08:00
write_driver.mag
Fix pin names to lower case. Fix write driver DRC errors and LVS error.
2018-01-31 17:37:16 -08:00
Powered by Gitea Version: 1.27.2 Page: 3428ms Template: 25ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API