Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
b912f289a6f7dfd5ffbfa93d53ed2c26015a6679
OpenRAM/technology/scn4m_subm/tech
T
History
Matt Guthaus c01f0f5274 Merge branch 'dev' into fix_rbl_cell_connections
2018-11-05 16:38:46 -08:00
..
__init__.py
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
LICENSE.txt
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
SCN4M_SUBM.20.tech
Update SCN4M_SUBM Magic tech file.
2018-11-05 13:31:53 -08:00
tech.py
Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.
2018-10-30 22:19:26 -07:00
Powered by Gitea Version: 1.27.2 Page: 281ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API