Michael Timothy Grimes b90f5c9a59 pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd ...

current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors
adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports

2018-02-08 14:21:15 -08:00

..

characterizer

Move info messages about modes to better locations.

2018-01-05 08:32:23 -08:00

gdsMill

Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947.

2017-12-12 15:50:45 -08:00

router

Fix unit tests to be DRC clean.

2017-06-07 10:29:53 -07:00

tests

pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd

2018-02-08 14:21:15 -08:00

verify

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

bank.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

bitcell_array.py

Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).

2017-11-09 11:13:44 -08:00

bitcell.py

Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.

2017-11-14 13:24:14 -08:00

contact.py

Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947.

2017-12-12 15:50:45 -08:00

control_logic.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

debug.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

delay_chain.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

design.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

example_config_freepdk45.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

example_config_scn3me_subm.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

geometry.py

Remove metal3 blanket blockage on library cells.

2017-12-19 09:55:59 -08:00

globals.py

Improve output format. Rename option to be more sensible.

2017-11-22 15:57:29 -08:00

hierarchical_decoder.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

hierarchical_predecode2x4.py

Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).

2017-11-09 11:13:44 -08:00

hierarchical_predecode3x8.py

Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).

2017-11-09 11:13:44 -08:00

hierarchical_predecode.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

hierarchy_layout.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

hierarchy_spice.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

lef.py

Remove metal3 blanket blockage on library cells.

2017-12-19 09:55:59 -08:00

ms_flop_array.py

Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).

2017-11-09 11:13:44 -08:00

ms_flop.py

Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).

2017-11-09 11:13:44 -08:00

openram.py

Move info messages about modes to better locations.

2018-01-05 08:32:23 -08:00

options.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

path.py

Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins.

2017-10-05 17:35:05 -07:00

pbitcell.py

pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd

2018-02-08 14:21:15 -08:00

pgate.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

pin_layout.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

pinv.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

pnand2.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

pnand3.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

pnor2.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

precharge_array.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

precharge.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

ptx.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

regress.sh

Add regress.sh script for convenience

2016-11-18 08:00:34 -08:00

replica_bitcell.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

replica_bitline.py

Remove nor_2 reference

2017-12-12 19:25:35 -08:00

route.py

Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.

2017-08-07 10:24:45 -07:00

sense_amp_array.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

sense_amp.py

Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.

2017-11-14 13:24:14 -08:00

single_level_column_mux_array.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

single_level_column_mux.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

sram.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

tri_gate_array.py

Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).

2017-11-09 11:13:44 -08:00

tri_gate.py

Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.

2017-11-14 13:24:14 -08:00

utils.py

Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947.

2017-12-12 15:50:45 -08:00

vector.py

Merge master branch into router

2017-01-09 14:04:37 -08:00

verilog.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

wire.py

Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function.

2017-10-06 15:30:15 -07:00

wordline_driver.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

write_driver_array.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

write_driver.py

Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.

2017-11-14 13:24:14 -08:00