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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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b841fd7ce3fdb74f6b2a9c98e56decaf5e98b8ff
OpenRAM
/
technology
/
scn4m_subm
T
History
mrg
b841fd7ce3
Replica bitcell array with arbitrary RBLs working
2019-07-10 15:56:51 -07:00
..
gds_lib
Add other SCMOS dummy cells
2019-07-03 14:28:12 -07:00
mag_lib
Replica bitcell array with arbitrary RBLs working
2019-07-10 15:56:51 -07:00
models
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
sp_lib
Add other SCMOS dummy cells
2019-07-03 14:28:12 -07:00
sue_lib
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
tf
Remove file named LICENSE since it is in the README for the tech files
2019-01-25 15:58:49 -08:00
__init__.py
Fix space before comment
2019-06-14 08:43:41 -07:00
