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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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b8061d3a4e03684ff22d9b5fe93d87cab2a774e3
OpenRAM/compiler/pgates
T
History
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline.
2018-11-08 23:54:18 -08:00
..
pgate.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pinv.py
Added initial code for determining the logical effort delay of the wordline.
2018-11-08 23:54:18 -08:00
pinvbuf.py
Added initial code for determining the logical effort delay of the wordline.
2018-11-08 23:54:18 -08:00
pnand2.py
Added initial code for determining the logical effort delay of the wordline.
2018-11-08 23:54:18 -08:00
pnand3.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
pnor2.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
precharge.py
Merge branch 'dev' into supply_routing
2018-10-17 09:47:18 -07:00
ptx.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
single_level_column_mux.py
Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell.
2018-11-02 05:59:47 -07:00
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