OpenRAM/compiler
Aditi Sinha b75eeb7688 Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
..
base Merge branch 'dev' into tech_migration 2020-03-05 14:18:06 -08:00
bitcells bitcell: Remove hardcoded signal pins 2020-02-12 15:37:51 +01:00
characterizer Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
datasheet Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
drc Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
example_configs revert example scn4m to non netlist only 2020-02-09 23:52:11 -08:00
gdsMill added purposes to addText(), removed reference to specific tech from gdsMill 2020-02-19 16:26:52 -08:00
modules Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
pgates Rotate via and PEP8 formatting 2020-03-06 13:39:46 -08:00
router tech: Make power_grid configurable 2020-01-28 12:06:34 +01:00
sram Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
tests Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
verify Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
gen_stimulus.py Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
globals.py Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
openram.py Characterization for extra rows 2020-02-20 17:01:52 +00:00
options.py Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram_factory.py sram_factory: Add check for duplicate module name 2019-12-19 16:31:52 +01:00
view_profile.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00