mirror of https://github.com/VLSIDA/OpenRAM.git
195 lines
6.2 KiB
Python
195 lines
6.2 KiB
Python
"""
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This is a DRC/LVS interface for Assura. It implements completely two
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functions: run_drc and run_lvs, that perform these functions in batch
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mode and will return true/false if the result passes. All of the setup
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(the rules, temp dirs, etc.) should be contained in this file.
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Replacing with another DRC/LVS tool involves rewriting this code to
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work properly. Porting to a new technology in Assura means pointing
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the code to the proper DRC and LVS rule files.
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LVS Notes:
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For some processes the FET models are sub-circuits. Meaning, the
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first letter of their SPICE instantiation begins with 'X' not 'M'.
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The former confuses Assura, however, so to get these sub-circuit models
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to LVS properly, an empty sub-circuit must be inserted into the
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LVS SPICE netlist. The sub-circuits are pointed to using the
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drc["lvs_subcircuits"] variable, and additional options must be
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inserted in the runset.
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"""
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import os
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import re
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import time
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import debug
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from globals import OPTS
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# Keep track of statistics
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num_drc_runs = 0
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num_lvs_runs = 0
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num_pex_runs = 0
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def run_drc(name, gds_name):
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"""Run DRC check on a given top-level name which is
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implemented in gds_name."""
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global num_drc_runs
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num_drc_runs += 1
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from tech import drc
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drc_rules = drc["drc_rules"]
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drc_runset = OPTS.openram_temp + name + ".rsf"
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drc_log_file = "{0}{1}.log".format(OPTS.openram_temp, name)
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# write the runset file
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# the runset file contains all the options to run Assura
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# different processes may require different options
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f = open(drc_runset, "w")
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f.write("avParameters(\n")
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f.write(" ?flagDotShapes t\n")
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f.write(" ?flagMalformed t\n")
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f.write(" ?flagPathNonManhattanSeg all\n")
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f.write(" ?flagPathShortSegments endOnlySmart\n")
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f.write(" ?maintain45 nil\n")
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f.write(" ?combineNearCollinearEdges nil\n")
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f.write(")\n")
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f.write("\n")
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f.write("avParameters(\n")
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f.write(" ?inputLayout ( \"gds2\" \"{}\" )\n".format(gds_name))
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f.write(" ?cellName \"{}\"\n".format(name))
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f.write(" ?workingDirectory \"{}\"\n".format(OPTS.openram_temp))
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f.write(" ?rulesFile \"{}\"\n".format(drc_rules))
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f.write(" ?set ( \"GridCheck\" )\n")
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f.write(" ?avrpt t\n")
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f.write(")\n")
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f.close()
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# run drc
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cwd = os.getcwd()
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os.chdir(OPTS.openram_temp)
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cmd = "assura {0} 2> {1} 1> {2}".format(drc_runset, drc_log_file, drc_log_file)
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debug.info(1, cmd)
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os.system(cmd)
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os.chdir(cwd)
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# count and report errors
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errors = 0
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try:
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f = open(OPTS.openram_temp+name+".err", "r")
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except:
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debug.error("Unable to retrieve DRC results file.",1)
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results = f.readlines()
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f.close()
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for line in results:
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if re.match("Rule No.", line):
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if re.search("# INFO:", line) == None:
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errors = errors + 1
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debug.info(1, line)
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if errors > 0:
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debug.error("Errors: {}".format(errors))
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return errors
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def run_lvs(name, gds_name, sp_name):
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"""Run LVS check on a given top-level name which is
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implemented in gds_name and sp_name. """
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global num_lvs_runs
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num_lvs_runs += 1
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from tech import drc
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lvs_rules = drc["lvs_rules"]
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lvs_runset = OPTS.openram_temp + name + ".rsf"
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# The LVS compare rules must be defined in the tech file for Assura.
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lvs_compare = drc["lvs_compare"]
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# Define the must-connect names for disconnected LVS nets for Assura
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lvs_bindings = drc["lvs_bindings"]
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lvs_log_file = "{0}{1}.log".format(OPTS.openram_temp, name)
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# Needed when FET models are sub-circuits
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if drc.has_key("lvs_subcircuits"):
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lvs_sub_file = drc["lvs_subcircuits"]
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else:
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lvs_sub_file = ""
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# write the runset file
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# the runset file contains all the options to run Assura
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# different processes may require different options
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f = open(lvs_runset, "w")
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f.write("avParameters(\n")
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f.write(" ?inputLayout ( \"gds2\" \"{}\" )\n".format(gds_name))
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f.write(" ?cellName \"{}\"\n".format(name))
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f.write(" ?workingDirectory \"{}\"\n".format(OPTS.openram_temp))
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f.write(" ?rulesFile \"{}\"\n".format(lvs_rules))
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f.write(" ?autoGrid nil\n")
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f.write(" ?avrpt t\n")
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# The below options vary greatly between processes and cell-types
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f.write(" ?set (\"NO_SUBC_IN_GRLOGIC\")\n")
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f.write(")\n")
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f.write("\n")
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c = open(lvs_compare, "r")
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lines = c.read()
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c.close
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f.write(lines)
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f.write("\n")
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f.write("avCompareRules(\n")
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f.write(" schematic(\n")
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# Needed when FET models are sub-circuits
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if os.path.isfile(lvs_sub_file):
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f.write(" genericDevice(emptySubckt)\n")
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f.write(" netlist( spice \"{}\" )\n".format(lvs_sub_file))
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f.write(" netlist( spice \"{}\" )\n".format(sp_name))
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f.write(" )\n")
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f.write(" layout(\n")
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# Separate gnd shapes are sometimes not connected by metal, so this connects by name
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# The use of this option is not recommended for final DRC
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f.write(" joinNets( root \"gnd\" \"gnd*\" ) \n")
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f.write(" )\n")
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f.write(" bindingFile( \"{}\" )\n".format(lvs_bindings))
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f.write(")\n")
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f.write("\n")
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f.write("avLVS()\n")
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f.close()
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# run lvs
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cwd = os.getcwd()
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os.chdir(OPTS.openram_temp)
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cmd = "assura {0} 2> {1} 1> {2}".format(lvs_runset, lvs_log_file, lvs_log_file)
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debug.info(1, cmd)
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os.system(cmd)
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os.chdir(cwd)
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errors = 0
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try:
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f = open(OPTS.openram_temp+name+".csm", "r")
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except:
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debug.error("Unable to retrieve LVS results file.",1)
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results = f.readlines()
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f.close()
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for line in results:
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if re.search("errors", line):
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errors = errors + 1
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debug.info(1, line)
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elif re.search("Schematic and Layout", line):
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debug.info(1, line)
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return errors
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def run_pex(name, gds_name, sp_name, output=None):
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"""Run pex on a given top-level name which is
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implemented in gds_name and sp_name. """
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debug.error("PEX extraction not implemented with Assura.",-1)
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global num_pex_runs
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num_pex_runs += 1
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def print_drc_stats():
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debug.info(1,"DRC runs: {0}".format(num_drc_runs))
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def print_lvs_stats():
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debug.info(1,"LVS runs: {0}".format(num_lvs_runs))
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def print_pex_stats():
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debug.info(1,"PEX runs: {0}".format(num_pex_runs))
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