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OpenRAM/compiler/bitcells
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Matt Guthaus 90d1fa7c43 Bitcell supply routing fixes. 
Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
 		2018-11-30 12:32:13 -08:00
..
bitcell.py Simplify bl and br name lists. 2018-11-08 15:48:49 -08:00
bitcell_1rw_1r.py Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
pbitcell.py Bitcell supply routing fixes. 2018-11-30 12:32:13 -08:00
replica_bitcell.py Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
replica_bitcell_1rw_1r.py Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
replica_pbitcell.py Move replica bitcells to new bitcells subdir 2018-10-24 09:06:29 -07:00