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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-09-01 18:48:10 +02:00
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b65ebc61603aadfd64c34b91cbb1ad01f43dce54
OpenRAM
/
technology
/
scn4m_subm
/
sp_lib
T
History
Bugra Onal
0ff1d1a23d
Added buff to sense_amp in scmos
2023-04-12 11:49:32 -07:00
..
cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
cell_6t.st0
…
dff.sp
…
dummy_cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
dummy_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
replica_cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
replica_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
sense_amp.sp
Added buff to sense_amp in scmos
2023-04-12 11:49:32 -07:00
tri_gate.sp
…
write_driver.sp
Remove unnecessary footer in write driver
2019-08-01 08:59:41 -07:00
