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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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b5e05ee7a97270b0101c35ea0755490ac442f2ba
OpenRAM/technology/scn4m_subm/sp_lib
T
History
Matt Guthaus b5e05ee7a9 Replace write driver with human readable sp file.
2018-11-27 11:42:58 -08:00
..
cell_1rw_1r.sp
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
dff.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
replica_cell_1rw_1r.sp
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
replica_cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
sense_amp.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tri_gate.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
write_driver.sp
Replace write driver with human readable sp file.
2018-11-27 11:42:58 -08:00
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