Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
b59c789dec692cee9843277f188486d621d3b35b
OpenRAM/compiler/sram
T
History
mrg f358de78bb Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
2020-04-03 13:39:54 -07:00
..
sram_1bank.py
Route RBL to edge of bank.
2020-03-06 09:03:52 -08:00
sram_2bank.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
sram_base.py
Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
2020-04-03 13:39:54 -07:00
sram_config.py
s8 gdsless netlist only working up to dff array
2020-02-09 21:37:09 -08:00
sram.py
PEP8 Formatting
2020-03-05 16:20:21 -08:00
Powered by Gitea Version: 1.27.2 Page: 423ms Template: 8ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API