mirror of https://github.com/VLSIDA/OpenRAM.git
208 lines
7.2 KiB
Python
Executable File
208 lines
7.2 KiB
Python
Executable File
import os
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"""
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Class containing the process technology parameters.
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"""
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info={}
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info["name"]="scn3me_subm"
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info["body_tie_down"] = 0
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info["has_pwell"] = True
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info["has_nwell"] = True
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#GDS file info
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GDS={}
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GDS["unit"]=(0.001,1e-6)
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#####################################################################################################
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##GDS Layer Map######################################################################################
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#####################################################################################################
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# create the GDS layer map
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layer={}
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layer["vtg"] = -1
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layer["vth"] = -1
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layer["contact"] = 25
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layer["pwell"] = 41
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layer["nwell"] = 42
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layer["active"] = 43
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layer["pimplant"] = 44
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layer["nimplant"] = 45
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layer["poly"] = 46
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layer["poly_contact"] = 47
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layer["active_contact"] = 48
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layer["metal1"] = 49
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layer["via1"] = 50
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layer["metal2"] = 51
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layer["via2"] = 61
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layer["metal3"] = 62
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layer["text"] = 83
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layer["boundary"] = 83
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#####################################################################################################
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##END GDS Layer Map##################################################################################
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#####################################################################################################
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#####################################################################################################
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##DRC/LVS Rules Setup################################################################################
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#####################################################################################################
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#technology parameter
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parameter={}
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parameter["min_tx_size"] = 1.2
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parameter["pinv_beta"] = 2 #for use in pinv
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drclvs_home=os.environ.get("DRCLVS_HOME")
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drc={}
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#grid size
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drc["grid"]=0.15
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#DRC/LVS test set_up
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drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
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drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
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drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/layers.map"
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# minwidth_tx withcontact
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drc["minwidth_tx"] = 1.2
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drc["minlength_channel"] = 0.6
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#well rules
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drc["pwell_enclose_nwell"] = 0
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drc["minwidth_well"] = 3.6
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#poly rules
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drc["minwidth_poly"] = 0.6
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drc["minheight_poly"] = 0.0
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drc["poly_to_poly"] = 0.9
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drc["poly_extend_active"] = 0.6
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drc["poly_to_polycontact"] = 1.2
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drc["active_enclosure_gate"] = 0.0
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drc["poly_to_active"] = 0.3
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drc["minarea_poly"] = 0.0
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#active
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drc["active_extend_gate"] = 0
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drc["active_to_body_active"] = 1.2 # Fix me
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drc["minwidth_active"] = 0.9
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drc["minheight_active"] = 0.9
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drc["minarea_active"] = 0.0
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drc["active_to_active"] = 0.9
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drc["well_enclosure_active"] = 1.8
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drc["well_extend_active"] = 1.8
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#Implant (None in IBM)
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drc["implant_to_gate"] = 0
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drc["implant_to_channel"] = 0
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drc["implant_to_contact"] = 0
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drc["implant_to_implant"] = 0
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drc["minwidth_implant"] = 0
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#Contact
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drc["minwidth_contact"] = 0.6
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drc["minwidth_active_contact"] = 0.6
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drc["minwidth_poly_contact"] = 0.6
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drc["active_enclosure_contact"] = 0.3
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drc["active_extend_contact"] = 0.3
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drc["poly_enclosure_contact"] = 0.3
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drc["poly_extend_contact"] = 0.3
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drc["contact_to_poly"] = 0.6
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drc["contact_to_contact"] = 0.9
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drc["active_contact_to_active_contact"] = 0.9
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drc["poly_contact_to_poly_contact"] = 0.9
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drc["active_extend_active_contact"] = 0.3
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drc["poly_extend_poly_contact"] = 0.3
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drc["active_enclosure_active_contact"] = 0.3
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drc["poly_enclosure_poly_contact"] = 0.3
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#Metal1
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drc["minwidth_metal1"] = 0.9
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drc["minheight_metal1"] = 0
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drc["metal1_to_metal1"] = 0.9
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drc["metal1_to_contact"] = 0.9
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drc["metal1_enclosure_contact"] = 0.3
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drc["metal1_extend_contact"] = 0.3
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drc["metal1_extend_via1"] = 0.3
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drc["metal1_enclosure_via1"] = 0.3
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drc["minarea_metal1"] = 0
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drc["metal1_enclosure_active_contact"] = 0.3
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drc["metal1_enclosure_poly_contact"] = 0.3
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drc["metal1_extend_active_contact"] = 0.3
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drc["metal1_extend_poly_contact"] = 0.3
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#via1
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drc["minwidth_via1"] = 0.6
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drc["via1_to_via1"] = 0.6
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drc["minselect_overlap_via1"] = 0.3 # Fix me
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#Metal2
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drc["minwidth_metal2"] = 0.9
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drc["minheight_metal2"] = 0
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drc["metal2_to_metal2"] = 0.9
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drc["metal2_extend_via1"] = 0.3
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drc["metal2_enclosure_via1"] = 0.3
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drc["metal2_extend_via2"] = 0.3
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drc["metal2_enclosure_via2"] = 0.3
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drc["minarea_metal2"] = 0
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#Via2
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drc["minwidth_via2"] = 0.6
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drc["via2_to_via2"] = 0.9
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#Metal3
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drc["minwidth_metal3"] = 1.5
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drc["minheight_metal3"] = 0.0
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drc["metal3_to_metal3"] = 0.9
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drc["metal3_extend_via2"] = 0.6
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drc["metal3_enclosure_via2"] = 0.6
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drc["minarea_metal3"] = 0
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#####################################################################################################
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##END DRC/LVS Rules##################################################################################
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#####################################################################################################
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#####################################################################################################
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##Spice Simulation Parameters########################################################################
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#####################################################################################################
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# spice model info
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spice={}
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spice["nmos"]="n"
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spice["pmos"]="p"
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spice["fet_models"] = [os.environ.get("SPICE_MODEL_DIR")+"/on_c5n.sp"]
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#spice stimulus related variables
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spice["clock_period"] = 10.0
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spice["supply_voltage"] = 5.0 #vdd in [Volts]
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spice["gnd_voltage"] = 0.0 #gnd in [Volts]
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spice["rise_time"] = 0.001 #rise time in [Nano-seconds]
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spice["fall_time"] = 0.001 #fall time in [Nano-seconds]
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spice["temp"] = 25 #temperature in [Celsius]
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#parasitics of metal for bit/word lines
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spice["bitline_res"] = 0.1 #bitline resistance in [Ohms/micro-meter]
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spice["bitline_cap"] = 0.2 #bitline capacitance in [Femto-farad/micro-meter]
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spice["wordline_res"] = 0.1 #wordline resistance in [Ohms/micro-meter]
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spice["wordline_cap"] = 0.2 #wordline capacitance in [Femto-farad/micro-meter]
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spice["FF_in_cap"] = 9.8242 #Input capacitance of ms_flop (Din) [Femto-farad]
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spice["tri_gate_out_cap"] = 1.4980 #Output capacitance of tri_gate (tri_out) [Femto-farad]
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#sram signal names
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spice["vdd_name"] = "vdd"
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spice["gnd_name"] = "gnd"
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spice["control_signals"] = ["CSb", "WEb", "OEb"]
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spice["data_name"] = "DATA"
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spice["addr_name"] = "ADDR"
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spice["pmos_name"] = spice["pmos"]
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spice["nmos_name"] = spice["nmos"]
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spice["minwidth_tx"] = drc["minwidth_tx"]
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spice["channel"] = drc["minlength_channel"]
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spice["clk"] = "clk"
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# estimated feasible period in ns
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spice["feasible_period"] = 5
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