mirror of https://github.com/VLSIDA/OpenRAM.git
79 lines
958 B
Verilog
79 lines
958 B
Verilog
module sram;
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reg [3:0] addr;
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reg [1:0] data;
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reg clk;
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reg csb;
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reg web;
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reg oeb;
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wire [1:0] data_in = !oeb ? 2'bzz : data;
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sram_2_16_1_freepdk45 U0 (.DATA(data_in),
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.ADDR(addr),
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.CSb (csb),
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.WEb (web),
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.OEb (oeb),
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.clk (clk)
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);
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initial
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begin
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$monitor("%g addr=%b data=%b",
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$time, addr, data_in,);
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clk = 0;
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csb = 1;
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web = 1;
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oeb = 1;
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addr = 0;
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data = 0;
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// write
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#10 data=2'b10;
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addr=4'h1;
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web = 0;
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oeb = 1;
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csb = 0;
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// write another
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#10 data=2'b01;
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addr=4'hC;
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web = 0;
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oeb = 1;
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csb = 0;
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// read undefined
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#10 data=2'b11;
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addr=4'h0;
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web = 1;
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oeb = 0;
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csb = 0;
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// read defined
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#10 data=2'b11;
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addr=4'hC;
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web = 1;
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oeb = 0;
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csb = 0;
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// read defined
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#10 data=2'b11;
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addr=4'h1;
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web = 1;
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oeb = 0;
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csb = 0;
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#30 $finish;
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end
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always
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#5 clk = !clk;
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endmodule
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