mirror of https://github.com/VLSIDA/OpenRAM.git
f48272bde6
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| .. | ||
| golden | ||
| 00_code_format_check_test.py | ||
| 01_library_drc_test.py | ||
| 02_library_lvs_test.py | ||
| 03_contact_test.py | ||
| 03_path_test.py | ||
| 03_ptx_1finger_nmos_test.py | ||
| 03_ptx_1finger_pmos_test.py | ||
| 03_ptx_3finger_nmos_test.py | ||
| 03_ptx_3finger_pmos_test.py | ||
| 03_wire_test.py | ||
| 04_nand_2_test.py | ||
| 04_nand_3_test.py | ||
| 04_nor_2_test.py | ||
| 04_pinv_test.py | ||
| 04_wordline_driver_test.py | ||
| 05_bitcell_array_test.py | ||
| 06_hierarchical_decoder_test.py | ||
| 06_hierarchical_predecode2x4_test.py | ||
| 06_hierarchical_predecode3x8_test.py | ||
| 07_single_level_column_mux_test.py | ||
| 08_precharge_array_test.py | ||
| 09_sense_amp_array_test.py | ||
| 10_write_driver_array_test.py | ||
| 11_ms_flop_array_test.py | ||
| 13_control_logic_test.py | ||
| 14_logic_effort_dc_test.py | ||
| 15_tri_gate_array_test.py | ||
| 16_replica_bitline_test.py | ||
| 19_bank_test.py | ||
| 20_sram_1bank_test.py | ||
| 20_sram_2bank_test.py | ||
| 20_sram_4bank_test.py | ||
| 21_timing_delay_test.py | ||
| 21_timing_hold_test.py | ||
| 21_timing_setup_test.py | ||
| 22_pex_func_test_with_pinv.py | ||
| 22_sram_func_test.py | ||
| 23_lib_sram_test.py | ||
| 24_lef_sram_test.py | ||
| 25_verilog_sram_test.py | ||
| 30_openram_test.py | ||
| README | ||
| config_20_freepdk45.py | ||
| config_20_scn3me_subm.py | ||
| header.py | ||
| regress.py | ||
| sram_2_16_1_freepdk45.gds | ||
| sram_2_16_1_freepdk45.lef | ||
| sram_tb.v | ||
README
Note that the tests turn off DRC/LVS when they perform their own check for performance improvement. However, it must be turned back on before the test runs an assert.