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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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b3fa6b9d5281fa36d6e4ef44aaef399a40e93fd3
OpenRAM/technology/scn3me_subm/tech
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Matt Guthaus f4389bdd8f Add extra track spacings in some routes.
2018-09-13 14:12:24 -07:00
..
__init__.py
Remove dead code ptx_port.
2018-01-19 16:19:05 -08:00
calibreDRC_scn3me_subm.rul
Add back scn3me_subm rule files
2016-11-09 09:32:26 -08:00
calibreLVS_scn3me_subm.rul
Add back scn3me_subm rule files
2016-11-09 09:32:26 -08:00
LICENSE.txt
Updated to include local magic rules
2018-08-15 09:46:23 -07:00
SCN3ME_SUBM.30.tech
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
tech.py
Add extra track spacings in some routes.
2018-09-13 14:12:24 -07:00
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