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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 19:18:39 +02:00
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b06aa84824747296d0dfbf7fd59ba1489df6c6bf
OpenRAM/technology/scn4m_subm/sp_lib
T
History
Hunter Nichols 80bc5b49c1 Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
2018-11-14 11:00:37 -08:00
..
cell_1rw_1r.sp
Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.
2018-11-13 22:24:18 -08:00
cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
dff.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
replica_cell_1rw_1r.sp
Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
2018-11-14 11:00:37 -08:00
replica_cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
sense_amp.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tri_gate.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
write_driver.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
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