Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.

2018-11-01 12:29:49 -07:00

..

bank_select.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

bank.py

Changed the analytical delay model to accept multiport options. Little substance to the values generated.

2018-10-26 00:08:13 -07:00

bitcell_array.py

Changed the analytical delay model to accept multiport options. Little substance to the values generated.

2018-10-26 00:08:13 -07:00

control_logic.py

Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.

2018-10-30 22:19:26 -07:00

delay_chain.py

Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.

2018-09-26 19:10:24 -07:00

dff_array.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

dff_buf_array.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

dff_buf.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_inv_array.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

dff_inv.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff.py

Remove ms_flop and replace with dff. Might break setup_hold tests.

2018-09-13 11:02:28 -07:00

hierarchical_decoder.py

Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias.

2018-10-20 12:54:12 -07:00

hierarchical_predecode2x4.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

hierarchical_predecode3x8.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

hierarchical_predecode.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

multibank.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

precharge_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

replica_bitline.py

Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.

2018-11-01 12:29:49 -07:00

sense_amp_array.py

Fixed spacing in golden lib files. Added column mux into analytical model.

2018-10-24 00:16:26 -07:00

sense_amp.py

Fixed import errors with mux analytical delay model.

2018-10-26 17:37:25 -07:00

single_level_column_mux_array.py

Fixed import errors with mux analytical delay model.

2018-10-26 17:37:25 -07:00

tri_gate_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

write_driver_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

write_driver.py

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