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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
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ab6afb7ca817bdedcd73ddbaec68599719aa25da
OpenRAM/technology/scn3me_subm/tech
T
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Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell.
2018-10-17 07:28:56 -07:00
..
__init__.py
Remove dead code ptx_port.
2018-01-19 16:19:05 -08:00
calibreDRC_scn3me_subm.rul
Add back scn3me_subm rule files
2016-11-09 09:32:26 -08:00
calibreLVS_scn3me_subm.rul
Add back scn3me_subm rule files
2016-11-09 09:32:26 -08:00
LICENSE.txt
Updated to include local magic rules
2018-08-15 09:46:23 -07:00
SCN3ME_SUBM.30.tech
Convert bounding box layer for SCMOS to bb, gds layer 63.
2018-09-04 13:05:21 -07:00
tech.py
adding 6T transistor size parameters to tech files for use in pbitcell.
2018-10-17 07:28:56 -07:00
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