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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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aa0d032c78ec621184d975502bd7887e09a87912
OpenRAM/compiler/characterizer
T
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Hunter Nichols aa0d032c78 Cleaned the char_data to fit the previous style. Added print statements to load/slew sims.
2018-10-04 14:04:08 -07:00
..
__init__.py
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Cleaned the char_data to fit the previous style. Added print statements to load/slew sims.
2018-10-04 14:04:08 -07:00
functional.py
Correcting functional inheritance from simulation.
2018-10-04 13:55:59 -07:00
lib.py
Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports.
2018-09-10 22:06:50 -07:00
setup_hold.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
simulation.py
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
stimuli.py
Correcting functional inheritance from simulation.
2018-10-04 13:55:59 -07:00
trim_spice.py
Convert bitline index to integer in trim_spice
2018-07-26 14:29:44 -07:00
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