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OpenRAM/technology/freepdk45/sp_lib
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mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 		2020-11-13 10:07:40 -08:00
..
cell_1rw.sp Rework bitcells. 2020-11-13 10:07:40 -08:00
cell_2rw.sp Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
dff.sp Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
dummy_cell_1rw.sp Rework bitcells. 2020-11-13 10:07:40 -08:00
dummy_cell_2rw.sp Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
replica_cell_1rw.sp Rework bitcells. 2020-11-13 10:07:40 -08:00
replica_cell_2rw.sp Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
sense_amp.sp Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
tri_gate.sp RELEASE 1.0 2016-11-08 09:57:35 -08:00
write_driver.sp Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00