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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-31 18:25:18 +02:00
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a65818815c67f9af65da60dd6fdf0b96c75151ab
OpenRAM/compiler/bitcells
T
History
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
..
bitcell_1rw_1r.py
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
bitcell_1w_1r.py
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
bitcell.py
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
pbitcell.py
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
replica_bitcell_1rw_1r.py
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
replica_bitcell_1w_1r.py
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
replica_bitcell.py
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
replica_pbitcell.py
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
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