mirror of https://github.com/VLSIDA/OpenRAM.git
60 lines
2.2 KiB
Python
60 lines
2.2 KiB
Python
# See LICENSE for licensing information.
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#
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#Copyright (c) 2016-2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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import globals
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import design
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from math import log
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import design
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from tech import GDS,layer,spice,parameter
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import utils
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class dff(design.design):
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"""
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Memory address flip-flop
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"""
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pin_names = ["D", "Q", "clk", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("dff", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"])
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def __init__(self, name="dff"):
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design.design.__init__(self, name)
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self.width = dff.width
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self.height = dff.height
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self.pin_map = dff.pin_map
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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c_eff = self.calculate_effective_capacitance(load)
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freq = spice["default_event_rate"]
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power_dyn = self.calc_dynamic_power(corner, c_eff, freq)
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power_leak = spice["msflop_leakage"]
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total_power = self.return_power(power_dyn, power_leak)
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return total_power
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def calculate_effective_capacitance(self, load):
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"""Computes effective capacitance. Results in fF"""
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from tech import parameter
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c_load = load
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c_para = spice["flop_para_cap"]#ff
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transition_prob = spice["flop_transition_prob"]
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return transition_prob*(c_load + c_para)
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def analytical_delay(self, corner, slew, load = 0.0):
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# dont know how to calculate this now, use constant in tech file
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result = self.return_delay(spice["dff_delay"], spice["dff_slew"])
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return result
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width.
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return parameter["dff_clk_cin"]
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