OpenRAM/compiler
mrg a5ed9b56cd Optional m4 in design class 2019-05-08 17:51:38 -07:00
..
base Optional m4 in design class 2019-05-08 17:51:38 -07:00
bitcells Update copyright to correct years. 2019-05-06 06:50:15 -07:00
characterizer Update copyright to correct years. 2019-05-06 06:50:15 -07:00
datasheet Update copyright to correct years. 2019-05-06 06:50:15 -07:00
drc Update copyright to correct years. 2019-05-06 06:50:15 -07:00
example_configs Add giant example for front-end mode 2019-04-01 15:49:01 -07:00
gdsMill Remove non-rectangular error and just skip them. 2019-01-30 10:25:01 -08:00
modules Update copyright to correct years. 2019-05-06 06:50:15 -07:00
pgates Update copyright to correct years. 2019-05-06 06:50:15 -07:00
router Update copyright to correct years. 2019-05-06 06:50:15 -07:00
tests Update copyright to correct years. 2019-05-06 06:50:15 -07:00
verify Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Makefile Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
debug.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
gen_stimulus.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
globals.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
openram.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
options.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
run_profile.sh Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
sram.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
sram_1bank.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
sram_2bank.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
sram_base.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
sram_config.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
sram_factory.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
view_profile.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00