Matt Guthaus a418431a42 First draft of sram_factory code		2019-01-16 16:15:38 -08:00
..
contact.py	Add m3m4 short hand in design class	2018-11-16 14:10:49 -08:00
design.py	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
geometry.py	Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.	2018-11-16 11:48:41 -08:00
hierarchy_design.py	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
hierarchy_layout.py	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00
hierarchy_spice.py	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
lef.py	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00
path.py	Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev	2018-02-09 10:25:28 -08:00
pin_layout.py	Fix instersection bug. Improve primary and secondary pin algo.	2018-12-04 16:53:04 -08:00
route.py	Remove diagonal routing bug. Cleanup.	2018-11-02 14:57:40 -07:00
utils.py	Allow multiple must-connect pins with the same label.	2018-11-07 13:05:13 -08:00
vector.py	Fix Future Warning for real	2018-10-10 15:58:16 -07:00
verilog.py	Remove tabs	2019-01-11 14:16:57 -08:00
wire.py	Update all drc usages to call function type	2018-10-12 14:37:51 -07:00