Matt Guthaus a2d8d16c7a Split DATA into DIN and DOUT in characterizer

2018-07-11 14:19:09 -07:00

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base

Modify unit tests to reset options during init_openram so

2018-07-10 16:39:32 -07:00

characterizer

Split DATA into DIN and DOUT in characterizer

2018-07-11 14:19:09 -07:00

gdsMill

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

modules

Push create bus functions down into layout class.

2018-07-10 10:06:59 -07:00

pgates

Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.

2018-06-29 11:49:02 -07:00

router

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tests

Disable LEF test until supplies fixed.

2018-07-11 14:18:53 -07:00

verify

Add DRC/LVS/PEX statistics in verbose=1 mode

2018-07-11 11:59:24 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

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example_config_scn3me_subm.py

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gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Fix order of checkpointing so that it is done after characterizer and verify have found their executables.

2018-07-11 12:12:03 -07:00

Makefile

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openram.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

options.py

Fix options so it is in /tmp in RAM drive

2018-07-05 16:33:26 -07:00

sram_1bank.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00

sram_2bank.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00

sram_4bank.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00

sram.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00