Matt Guthaus a2b1d025ab Merge multiport

2018-10-08 11:45:50 -07:00

..

bank_select.py

Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport.

2018-09-27 02:01:32 -07:00

bank.py

Merge multiport

2018-10-08 11:45:50 -07:00

bitcell_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

control_logic.py

Removing we_b signal from write ports since it is redundant.

2018-10-04 09:31:04 -07:00

delay_chain.py

Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.

2018-09-26 19:10:24 -07:00

dff_array.py

Move clk up in dff arrays for supply pin access

2018-10-05 08:18:38 -07:00

dff_buf_array.py

Move clk up in dff arrays for supply pin access

2018-10-05 08:18:38 -07:00

dff_buf.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_inv_array.py

Move clk up in dff arrays for supply pin access

2018-10-05 08:18:38 -07:00

dff_inv.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff.py

Remove ms_flop and replace with dff. Might break setup_hold tests.

2018-09-13 11:02:28 -07:00

hierarchical_decoder.py

Make bitcell width/height not static. Update modules to use it for pbitcell.

2018-09-04 11:55:22 -07:00

hierarchical_predecode2x4.py

Converted all modules to not run create_layout when netlist_only

2018-08-27 16:42:48 -07:00

hierarchical_predecode3x8.py

Converted all modules to not run create_layout when netlist_only

2018-08-27 16:42:48 -07:00

hierarchical_predecode.py

Add extra track spacings in some routes.

2018-09-13 14:12:24 -07:00

multibank.py

Updating ms_flop removal.

2018-09-13 11:40:24 -07:00

precharge_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

replica_bitcell.py

Finish renaming replica bitcell and bitline pin names.

2018-09-04 14:03:15 -07:00

replica_bitline.py

Adding mutliport constants to design.py to reduce the need for copied code across multiple modules.

2018-09-28 00:11:39 -07:00

replica_pbitcell.py

Correcting format of replica_pbitcell.

2018-09-13 18:51:52 -07:00

sense_amp_array.py

Make bitcell width/height not static. Update modules to use it for pbitcell.

2018-09-04 11:55:22 -07:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.

2018-09-09 22:06:29 -07:00

tri_gate_array.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.

2018-09-09 22:06:29 -07:00

write_driver_array.py

Make bitcell width/height not static. Update modules to use it for pbitcell.

2018-09-04 11:55:22 -07:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00