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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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a1ca7c312dbccd6c4d30c9d357ac01f85abd19c5
OpenRAM/technology/freepdk45/sp_lib
T
History
ota2 15e57d89ca fix end subckt typo
2021-02-27 18:28:07 -05:00
..
cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
dff.sp
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
dummy_cell_1rw.sp
fix end subckt typo
2021-02-27 18:28:07 -05:00
dummy_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
replica_cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
replica_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
sense_amp.sp
Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
2018-02-02 14:08:56 -08:00
tri_gate.sp
…
write_driver.sp
Change wen to en in spice lib files. Check lvs report insted of stdout with netgen.
2018-02-01 05:38:48 -08:00
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