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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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a164a14b3f1f34d2dcea85b97d10e2ab3750b976
OpenRAM/compiler/characterizer
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mguthaus f3efb5fb50 Fixed leakage and power unit test results.
2018-02-23 15:20:52 -08:00
..
__init__.py
Fail simulation tests if correct spice is not found. Correctly load spice characterizer.
2018-01-26 13:00:25 -08:00
charutils.py
Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit.
2018-02-21 13:38:43 -08:00
delay.py
Fixed leakage and power unit test results.
2018-02-23 15:20:52 -08:00
lib.py
Fixed leakage and power unit test results.
2018-02-23 15:20:52 -08:00
setup_hold.py
Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit.
2018-02-21 13:38:43 -08:00
stimuli.py
Change BSIM3 models to version 3.3.0. Add comment about multithreading selection.
2018-02-21 17:50:12 -08:00
trim_spice.py
Move delay-specific stimulus commands to delay.py. Keep stimuli.py generic.
2018-02-07 12:58:47 -08:00
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