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OpenRAM
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OpenRAM/compiler/tests
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Matt Guthaus 3f2b7b837d Skip multibank for now too 2018-10-10 16:57:42 -07:00
..
golden Convert unit tests to scn4m_subm 2018-09-17 11:13:46 -07:00
00_code_format_check_test.py
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01_library_drc_test.py
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02_library_lvs_test.py
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03_contact_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
03_path_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
03_ptx_1finger_nmos_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
03_ptx_1finger_pmos_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
03_ptx_3finger_nmos_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
03_ptx_3finger_pmos_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
03_ptx_4finger_nmos_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
03_ptx_4finger_pmos_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
03_wire_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_pbitcell_test.py Change options in pbitcell test to be global again. 2018-09-05 10:59:41 -07:00
04_pinv_1x_beta_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_pinv_1x_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_pinv_2x_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_pinv_10x_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_pinvbuf_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_pnand2_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_pnand3_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_pnor2_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
04_precharge_test.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
04_replica_pbitcell_test.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
04_single_level_column_mux_test.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
05_bitcell_array_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
05_pbitcell_array_test.py Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
06_hierarchical_decoder_test.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
06_hierarchical_predecode2x4_test.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
06_hierarchical_predecode3x8_test.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
07_single_level_column_mux_array_test.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
08_precharge_array_test.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
08_wordline_driver_test.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
09_sense_amp_array_test.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
10_write_driver_array_test.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
11_dff_array_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
11_dff_buf_array_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
11_dff_buf_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
11_dff_inv_array_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
11_dff_inv_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
12_tri_gate_array_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
13_delay_chain_test.py Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
14_replica_bitline_test.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
16_control_logic_test.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
19_bank_select_test.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
19_multi_bank_test.py Skip multibank for now too 2018-10-10 16:57:42 -07:00
19_pmulti_bank_test.py Skip pmulti which has LVS fail 2018-10-10 16:01:55 -07:00
19_psingle_bank_test.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
19_single_bank_test.py Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
20_psram_1bank_test.py Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
20_sram_1bank_2mux_test.py Separate 1bank tests 2018-10-10 15:58:00 -07:00
20_sram_1bank_4mux_test.py Separate 1bank tests 2018-10-10 15:58:00 -07:00
20_sram_1bank_8mux_test.py Separate 1bank tests 2018-10-10 15:58:00 -07:00
20_sram_1bank_nomux_test.py Separate 1bank tests 2018-10-10 15:58:00 -07:00
20_sram_2bank_test.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
20_sram_4bank_test.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
21_hspice_delay_test.py Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
21_hspice_setuphold_test.py Convert unit tests to scn4m_subm 2018-09-17 11:13:46 -07:00
21_ngspice_delay_test.py Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
21_ngspice_setuphold_test.py Convert unit tests to scn4m_subm 2018-09-17 11:13:46 -07:00
22_hspice_psram_func_test.py Skip func tests that are failing 2018-10-10 16:00:21 -07:00
22_hspice_sram_func_test.py Skip func tests that are failing 2018-10-10 16:00:21 -07:00
22_ngspice_psram_func_test.py Skip func tests that are failing 2018-10-10 16:00:21 -07:00
22_ngspice_sram_func_test.py Skip func tests that are failing 2018-10-10 16:00:21 -07:00
23_lib_sram_model_test.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
23_lib_sram_prune_test.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
23_lib_sram_test.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
24_lef_sram_test.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
25_verilog_sram_test.py Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
26_pex_test.py Renaming functional tests to include spice exe used. Renaming pex test to separate functional tests from pex test. 2018-09-30 22:39:37 -07:00
30_openram_test.py
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config_20_freepdk45.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
config_20_scn3me_subm.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
config_20_scn4m_subm.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00
regress.py
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testutils.py Rewrote pin enclosure code to better address off grid pins. 2018-10-10 15:15:58 -07:00