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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 11:08:01 +02:00
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9f7426052de24cef34ace79ddf8887f44cd8a4b4
OpenRAM/technology/scn4m_subm/gds_lib
T
History
mrg f7e3672c89 Route horizontal supplies in write driver.
2022-03-01 14:37:51 -08:00
..
cell_1rw.gds
Rework bitcells.
2020-11-13 10:07:40 -08:00
cell_2rw.gds
Route horizontal supplies in write driver.
2022-03-01 14:37:51 -08:00
dff.gds
update gds library, generalize geometry reverse transform function
2019-12-24 05:01:55 +00:00
dummy_cell_1rw.gds
Rework bitcells.
2020-11-13 10:07:40 -08:00
dummy_cell_2rw.gds
Route horizontal supplies in write driver.
2022-03-01 14:37:51 -08:00
replica_cell_1rw.gds
Remove label Q_bar from replica_cell_1rw due to Magic port bug
2022-01-13 14:38:59 -08:00
replica_cell_2rw.gds
Route horizontal supplies in write driver.
2022-03-01 14:37:51 -08:00
sense_amp.gds
update gds library, generalize geometry reverse transform function
2019-12-24 05:01:55 +00:00
tri_gate.gds
update gds library, generalize geometry reverse transform function
2019-12-24 05:01:55 +00:00
write_driver.gds
Add missing well tap
2022-02-25 10:44:40 -08:00
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