Jesse Cirimelli-Low 9501b99df7 merged branch wtih dev

2018-12-03 09:47:34 -08:00

..

base

merged branch wtih dev

2018-12-03 09:47:34 -08:00

bitcells

Bitcell supply routing fixes.

2018-11-30 12:32:13 -08:00

characterizer

merged branch wtih dev

2018-12-03 09:47:34 -08:00

datasheet

added css style code

2018-11-28 17:21:50 -08:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

gdsMill

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

modules

Bitcell supply routing fixes.

2018-11-30 12:32:13 -08:00

pgates

pgate inputs and outputs are all on M1 for flexible via placement when using gates.

2018-11-28 12:42:29 -08:00

router

Use grid furthest from blockages when blocked pin. Enclose multiple connectors.

2018-11-19 17:32:55 -08:00

tests

merged branch wtih dev

2018-12-03 09:47:34 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

example_config_scn4m_subm.py

Revert to 5V example until we fix spice models in scn4m_subm

2018-11-27 14:17:06 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py

2018-11-15 10:45:33 -08:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00

options.py

Remove local temp dir

2018-11-28 17:04:53 -08:00

sram_1bank.py

Convert channel router to take netlist of pins rather than names.

2018-11-29 12:12:10 -08:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_base.py

Fix SRAM level control routing errors.

2018-11-28 15:30:52 -08:00

sram_config.py

Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

sram.py

merged branch wtih dev

2018-12-03 09:47:34 -08:00