mirror of https://github.com/VLSIDA/OpenRAM.git
102 lines
4.0 KiB
Python
102 lines
4.0 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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import debug
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import utils
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from tech import GDS,layer, parameter,drc
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from tech import cell_properties as props
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from globals import OPTS
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import logical_effort
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class sense_amp(design.design):
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"""
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This module implements the single sense amp cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library.
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Sense amplifier to read a pair of bit-lines.
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"""
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pin_names = [props.sense_amp.pin.bl,
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props.sense_amp.pin.br,
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props.sense_amp.pin.dout,
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props.sense_amp.pin.en,
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props.sense_amp.pin.vdd,
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props.sense_amp.pin.gnd]
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type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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if not OPTS.netlist_only:
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(width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"])
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else:
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(width, height) = (0,0)
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pin_map = []
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def get_bl_names(self):
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return props.sense_amp.pin.bl
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def get_br_names(self):
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return props.sense_amp.pin.br
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@property
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def dout_name(self):
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return props.sense_amp.pin.dout
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@property
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def en_name(self):
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return props.sense_amp.pin.en
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def __init__(self, name):
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design.design.__init__(self, name)
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debug.info(2, "Create sense_amp")
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self.width = sense_amp.width
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self.height = sense_amp.height
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self.pin_map = sense_amp.pin_map
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self.add_pin_types(self.type_list)
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def get_cin(self):
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# FIXME: This input load will be applied to both the s_en timing and bitline timing.
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#Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
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from tech import spice, parameter
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# Default is 8x. Per Samira and Hodges-Jackson book:
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# "Column-mux transistors driven by the decoder must be sized for optimal speed"
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bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
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return spice["min_tx_drain_c"]*(bitline_pmos_size)#ff
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def get_stage_effort(self, load):
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#Delay of the sense amp will depend on the size of the amp and the output load.
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parasitic_delay = 1
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cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"])/drc("minwidth_tx")
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sa_size = parameter["sa_inv_nmos_size"]/drc("minwidth_tx")
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cc_inv_cin = cin
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return logical_effort.logical_effort('column_mux', sa_size, cin, load+cc_inv_cin, parasitic_delay, False)
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def analytical_power(self, corner, load):
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"""Returns dynamic and leakage power. Results in nW"""
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#Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
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total_power = self.return_power()
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return total_power
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def get_en_cin(self):
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"""Get the relative capacitance of sense amp enable gate cin"""
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pmos_cin = parameter["sa_en_pmos_size"]/drc("minwidth_tx")
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nmos_cin = parameter["sa_en_nmos_size"]/drc("minwidth_tx")
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#sen is connected to 2 pmos isolation TX and 1 nmos per sense amp.
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return 2*pmos_cin + nmos_cin
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def get_enable_name(self):
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"""Returns name used for enable net"""
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#FIXME: A better programmatic solution to designate pins
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enable_name = self.en_name
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debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name))
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return enable_name
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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