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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 01:24:39 +02:00
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9321f0461b97d1e57307a7f0aec6569a7afac4e4
OpenRAM
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technology
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scn4m_subm
T
History
Hunter Nichols
9321f0461b
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
..
gds_lib
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
mag_lib
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
models
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
sp_lib
Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r.
2018-10-31 00:06:34 -07:00
sue_lib
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech
Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.
2018-10-30 22:19:26 -07:00
tf
Supply router working except:
2018-09-18 12:57:39 -07:00
