Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
91a63fb5c2effc588ab179c53dae953e232cf4a3
OpenRAM/compiler/datasheet
T
History
Jesse Cirimelli-Low 5c4ee911aa added another VLSI logo and fixed control port numbering
2018-11-11 07:22:13 -08:00
..
assets
changed css to orange and black for Halloween; fixed CSb timing table in datasheet
2018-10-30 22:56:13 -07:00
characterization_corners.py
added docstring and renamed some functions
2018-10-30 21:37:30 -07:00
datasheet_gen.py
Complete rewrite of parser, all ports (except clock) added on multiport sheets
2018-11-10 20:23:26 -08:00
datasheet.py
added another VLSI logo and fixed control port numbering
2018-11-11 07:22:13 -08:00
deliverables.py
added docstring and renamed some functions
2018-10-30 21:37:30 -07:00
in_out.py
added docstring and renamed some functions
2018-10-30 21:37:30 -07:00
operating_conditions.py
added docstring and renamed some functions
2018-10-30 21:37:30 -07:00
timing_and_current_data.py
added docstring and renamed some functions
2018-10-30 21:37:30 -07:00
wavedrom.py
Complete rewrite of parser, all ports (except clock) added on multiport sheets
2018-11-10 20:23:26 -08:00
Powered by Gitea Version: 1.27.2 Page: 687ms Template: 11ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API