mirror of https://github.com/VLSIDA/OpenRAM.git
DRC/LVS passing for all parameterized gates. Magic and GDS match for SCMOS rules again. |
||
|---|---|---|
| .. | ||
| cell_6t.gds | ||
| ms_flop.gds | ||
| replica_cell_6t.gds | ||
| sense_amp.gds | ||
| tri_gate.gds | ||
| write_driver.gds | ||