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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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8ee6d3be6c9deab0d7a7710399c2d6568cd1ac86
OpenRAM/compiler/bitcells
T
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Hunter Nichols b408a871f9 Added direction information functions to 2-port bitcell modules
2021-06-21 17:19:15 -07:00
..
bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
bitcell_2port.py
Added direction information functions to 2-port bitcell modules
2021-06-21 17:19:15 -07:00
bitcell_base.py
Update copyright year.
2021-01-22 11:23:28 -08:00
col_cap_bitcell_1port.py
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2021-01-22 11:23:28 -08:00
col_cap_bitcell_2port.py
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2021-01-22 11:23:28 -08:00
dummy_bitcell_1port.py
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2021-01-22 11:23:28 -08:00
dummy_bitcell_2port.py
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2021-01-22 11:23:28 -08:00
dummy_pbitcell.py
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2021-01-22 11:23:28 -08:00
pbitcell.py
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2021-01-22 11:23:28 -08:00
replica_bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
replica_bitcell_2port.py
Added direction information functions to 2-port bitcell modules
2021-06-21 17:19:15 -07:00
replica_pbitcell.py
Update copyright year.
2021-01-22 11:23:28 -08:00
row_cap_bitcell_1port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
row_cap_bitcell_2port.py
Update copyright year.
2021-01-22 11:23:28 -08:00
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