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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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8e243258e491269eddb9735687912162f93cb524
OpenRAM/technology
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Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.
2018-10-26 00:08:12 -07:00
..
freepdk45
Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.
2018-10-26 00:08:12 -07:00
scn3me_subm
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
scn4m_subm
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
setup_scripts
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
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