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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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87419bd640505ddf496fed07a968346cd5b44088
OpenRAM/technology/scn4m_subm
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mrg 87419bd640 Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
..
gds_lib
add multiport support for pex labels
2020-01-28 00:28:55 +00:00
mag_lib
fix merge conflicts
2020-07-21 11:38:34 -07:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sp_lib
fix custom bitcell labeling; fix gds scaling in labeling
2020-01-15 09:00:02 +00:00
sue_lib
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
tf
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
__init__.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
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