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luke
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OpenRAM
mirror of
https://github.com/VLSIDA/OpenRAM.git
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8719a19377
OpenRAM
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compiler
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verify
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Matt Guthaus
33b04bbca5
Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.
2018-02-05 16:02:57 -08:00
..
__init__.py
Only check if using magic with freepdk when LVSDRC is enabled.
2018-01-17 07:38:29 -08:00
assura.py
Improve global and code structure using modules.
2017-11-16 13:52:58 -08:00
calibre.py
Disable virtual connects at top level LVS with Calibre.
2018-02-05 14:52:51 -08:00
magic.py
Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements.
2018-02-05 16:02:57 -08:00