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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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858fbb062d44abdf6f8fbe56b4433ca81a427264
OpenRAM/compiler/characterizer
T
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jsowash 2573b5f48b Fixed merge conflict.
2019-08-11 14:39:36 -07:00
..
__init__.py
Removed unused characterization module.
2019-07-30 20:33:17 -07:00
bit_polarity.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
charutils.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
delay.py
Redo logic for detecting bad bitlines
2019-08-10 17:32:36 -07:00
functional.py
Begin implementing a write mask layout as the port data level.
2019-08-07 09:12:21 -07:00
lib.py
…
logical_effort.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
measurements.py
…
model_check.py
…
setup_hold.py
…
simulation.py
Additional debug. Smaller psram func tests.
2019-08-05 13:53:14 -07:00
sram_op.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
stimuli.py
…
trim_spice.py
…
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